A 3.3-V 12-b 50-MS/s A/D converter in 0.6-/spl mu/m CMOS with over 80-dB SFDR

Author

Pan, Hui ; Segami, Masahiro ; Choi, Michael ; Cao, Jing ; Abidi, Asad A.

Author_Institution

Broadcom Corp., Irvine, CA, USA

Volume

35

Issue

12

fYear

2000

Firstpage

1769

Lastpage

1780

Abstract

A 12-b analog-to-digital converter (ADC) is optimized for spurious-free dynamic range (SFDR) performance at low supply voltage and suitable for use in modern wireless base stations. The 6-7-b two-stage pipeline ADC uses a bootstrap circuit to linearize the sampling switch of an on-chip sample-and-hold (S/H) and achieves over 80-dB SFDR for signal frequencies up to 75 MHz at 50 MSample/s (MSPS) without trimming, calibration, or dithering. INL is 1.3 LSB, differential nonlinearity (DNL) is 0.8 LSB. The 6-b and 7-b flash sub-ADCs are implemented efficiently using offset averaging and analog folding. In 0.6-/spl mu/m CMOS, the 16-mm/sup 2/ ADC dissipates 850 mW.

Keywords

CMOS integrated circuits; analogue-digital conversion; bootstrap circuits; pipeline processing; sample and hold circuits; 0.6 micron; 12 bit; 3.3 V; 850 mW; A/D converter; CMOS; INL; SFDR; analog folding; bootstrap circuit; differential nonlinearity; offset averaging; on-chip sample-and-hold; sampling switch; signal frequencies; supply voltage; two-stage pipeline circuit; wireless base stations; Analog-digital conversion; Base stations; Calibration; Dynamic range; Frequency; Low voltage; Pipelines; Sampling methods; Switches; Switching circuits;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.890290

Filename

890290