Title :
A 14-bit 100-Msample/s subranging ADC
Author :
Moreland, Carl ; Murden, Frank ; Elliott, Michael ; Young, Joe ; Hensley, Mike ; Stop, Russell
Author_Institution :
Analog Devices, Greensboro, NC, USA
Abstract :
This paper describes a 14-b analog-to-digital converter designed in a complementary bipolar process. Although it uses a fairly traditional three-stage subranging architecture, several nontraditional techniques are incorporated to achieve 14 bits of performance at a clock rate of 100 MHz. For linearity, the most critical of these is wafer level trimming of the first subrange digital-to-analog converter. Prototype silicon exhibits a spurious-free dynamic range of 90 dB through the Nyquist frequency and a signal-to noise ratio of 74 dB while dissipating 1.25 W.
Keywords :
analogue-digital conversion; bipolar integrated circuits; sample and hold circuits; 1.25 W; 100 MHz; 14 bit; Nyquist frequency; complementary bipolar process; signal-to noise ratio; spurious-free dynamic range; subranging ADC; three-stage subranging architecture; wafer level trimming; Analog-digital conversion; Bandwidth; Circuits; Clocks; Digital-analog conversion; Dynamic range; Error correction; Linearity; Prototypes; Silicon;
Journal_Title :
Solid-State Circuits, IEEE Journal of