Title :
A 90-dB SNR 2.5-MHz output-rate ADC using cascaded multibit delta-sigma modulation at 8/spl times/ oversampling ratio
Author :
Fujimori, Ichiro ; Longo, Lorenzo ; Hairapetian, Armond ; Seiyama, Kazushi ; Kosic, Steve ; Cao, Jun ; Chan, Shu-lap
Author_Institution :
Newport Commun., Irvine, CA, USA
Abstract :
A 16-b 2.5-MHz output-rate analog-to-digital converter (ADC) for wireline communications and high-speed instrumentation has been developed. A 2-1-1 cascaded delta-sigma modulator (DSM) employing 4-b quantizers in every stage makes all quantization noise sources negligible at 8/spl times/ oversampling ratio, Data weighted averaging with bi-directional rotation eliminates tones generated by multibit digital-to-analog converter (DAC) nonlinearity to increase the spurious-free dynamic-range (SFDR). Switched-capacitor design techniques using low-threshold transistors reduce front-end sampling distortion. The 24.8 mm/sup 2/ chip in 0.5-/spl mu/m CMOS also integrates the decimation filter and voltage reference. The ADC achieves 90-dB signal-to-noise ratio (SNR) in the 1.25-MHz bandwidth and 102-dB SFDR with 270-mW power dissipation.
Keywords :
CMOS integrated circuits; cascade networks; delta-sigma modulation; quantisation (signal); reference circuits; switched capacitor networks; 0.5 micron; 1.25 MHz; 16 bit; 2.5 MHz; 270 mW; ADC; CMOS; bi-directional rotation; cascaded multibit delta-sigma modulation; data weighted averaging; decimation filter; front-end sampling distortion; high-speed instrumentation; low-threshold transistors; oversampling ratio; power dissipation; quantization noise sources; signal-to-noise ratio; spurious-free dynamic-range; switched-capacitor design techniques; voltage reference; wireline communications; Analog-digital conversion; Bidirectional control; Communication switching; Delta modulation; Digital modulation; Digital-analog conversion; Instruments; Noise generators; Quantization; Signal to noise ratio;
Journal_Title :
Solid-State Circuits, IEEE Journal of
