A high-performance multibit /spl Delta//spl Sigma/ CMOS ADC

The design of a multibit /spl Delta//spl Sigma/ converter is presented. It uses a third-order 4-bit /spl Delta//spl Sigma/ topology with data weighted averaging (DWA) to reduce the linearity requirements of the digital-to-analog converters in the feedback loop. The implementation of the DWA algorithm is optimized to minimize the delay introduced in the feedback loop, resulting in clock frequencies up to 100 MHz. Behavioral models are used to determine several building block specifications. An accurate model is used to analyze the combined effect of the dominant closed loop pole of the operational transconductance amplifier (OTA), the slew rate and the nonzero switch resistance. It is shown that the offset requirements for the quantizer result in a large input capacitance of the quantizer. Therefore scaling of the OTAs, as classically employed in single-bit /spl Delta//spl Sigma/ converters, can no longer be used. For an oversampling ratio of only 24, the converter achieves a signal-to-noise ratio of 95 dB, a signal-to-noise-plus-distortion ratio of 89 dB and an input dynamic range of 97 dB after comb-filtering. The converter is sampled at 60 MHz, resulting in a 2.5 MS/s output rate. It is implemented in a standard 0.65-/spl mu/m CMOS technology, occupies 5.3 mm/sup 2/ and consumes 295 mW from a 5-V power supply. When clocked at 100 MHz with an oversampling ratio of 8, a 12-bit resolution is achieved at an output rate of 12.5 MS/s.