DocumentCode
1417226
Title
A CMOS nested-chopper instrumentation amplifier with 100-nV offset
Author
Bakker, Anton ; Thiele, Kevin ; Huijsing, Johan H.
Author_Institution
Philips Semicond., Sunnyvale, CA, USA
Volume
35
Issue
12
fYear
2000
Firstpage
1877
Lastpage
1883
Abstract
A CMOS nested-chopper instrumentation amplifier is presented with a typical offset of 100 nV. This performance is obtained by nesting an additional low-frequency chopper pair around a conventional chopper amplifier. The inner chopper pair removes the 1/f noise, while the outer chopper pair reduces the residual offset. The test chip is free from 1/f noise and has a thermal noise of 27 nV//spl radic/Hz consuming a total supply current of 200 /spl mu/A.
Keywords
1/f noise; CMOS analogue integrated circuits; choppers (circuits); instrumentation amplifiers; integrated circuit noise; interference suppression; 1/f noise removal; 100 nV; 200 muA; CMOS instrumentation amplifier; low-frequency chopper pair; nested-chopper instrumentation amplifier; offset cancellation; residual offset reduction; CMOS technology; Choppers; Frequency; Instruments; Low-frequency noise; Low-noise amplifiers; Noise cancellation; Noise reduction; Operational amplifiers; Semiconductor device noise;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/4.890300
Filename
890300
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