Energy-Efficient Neuron, Synapse and STDP Integrated Circuits

Author

Cruz-Albrecht, J.M. ; Yung, M.W. ; Srinivasa, N.

Author_Institution

Microelectron. Lab., HRL Labs. LLC, Malibu, CA, USA

Volume

6

Issue

3

fYear

2012

fDate

6/1/2012 12:00:00 AM

Firstpage

246

Lastpage

256

Abstract

Ultra-low energy biologically-inspired neuron and synapse integrated circuits are presented. The synapse includes a spike timing dependent plasticity (STDP) learning rule circuit. These circuits have been designed, fabricated and tested using a 90 nm CMOS process. Experimental measurements demonstrate proper operation. The neuron and the synapse with STDP circuits have an energy consumption of around 0.4 pJ per spike and synaptic operation respectively.

Keywords

CMOS integrated circuits; biomimetics; neural nets; 90 nm CMOS process; STDP integrated circuits; STDP learning rule circuit; energy-efficient neuron integrated circuits; spike timing dependent plasticity; synapse integrated circuits; ultra-low energy biologically-inspired neuron; Capacitors; Integrated circuit modeling; Neurons; Timing; Transconductance; Transistors; Brain; CMOS; energy; learning; low power electronics; neurons; spike timing dependent plasticity (STDP); synapses; Biomedical Engineering; Brain; Computers; Electrodes, Implanted; Electronics; Equipment Design; Humans; Models, Neurological; Neural Networks (Computer); Neurons; Prostheses and Implants; Signal Processing, Computer-Assisted; Synapses; Synaptic Transmission;

fLanguage

English

Journal_Title

Biomedical Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

1932-4545

Type

jour

DOI

10.1109/TBCAS.2011.2174152

Filename

6126001