Title :
A 0.6-W 10-Gb/s SONET/SDH bit-error-rate monitoring LSI
Author :
Kawai, Kenji ; Ichino, Haruhiko
Author_Institution :
Network Innovation Labs., Nippon Telegraph & Telephone Corp., Kanagawa, Japan
Abstract :
A 10-Gb/s SONET/SDH bit-error-rate monitoring LSI is fabricated by Si bipolar process. A byte-aligning demux architecture based on tree-type demux and clock inversions by detecting inversion indicating patterns reduces the power to only 14% of that of the previous chip. The LSI dissipates 0.6 W with -3.3-V supply voltage.
Keywords :
SONET; bipolar digital integrated circuits; demultiplexing equipment; large scale integration; low-power electronics; synchronous digital hierarchy; -3.3 V; 0.6 W; 10 Gbit/s; SONET/SDH; bipolar process; bit-error-rate monitoring LSI; byte-aligning demux architecture; clock inversions; inversion indicating patterns; power dissipation; tree-type demux; Bit error rate; Circuit faults; Large scale integration; Monitoring; Power dissipation; SONET; Spine; Synchronous digital hierarchy; WDM networks; Wavelength division multiplexing;
Journal_Title :
Solid-State Circuits, IEEE Journal of
