Title :
A 256/spl times/256 CMOS differential passive pixel imager with FPN reduction techniques
Author :
Fujimori, Iliana L. ; Wang, Ching-Chun ; Sodini, Charles G.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA
Abstract :
A 256/spl times/256 passive pixel imager has been implemented in a CMOS 0.6-/spl mu/m technology. A column-parallel differential architecture with a correlated double-sampling output circuit removes the smear-like effects of a parasitic current that plagues passive pixels, 0.1% pixel-to-pixel and 0.4% column-to-column fixed-pattern noise are achieved.
Keywords :
CMOS image sensors; integrated circuit noise; interference suppression; signal sampling; 0.6 micron; 256 pixel; 65536 pixel; CMOS imager; FPN reduction techniques; blooming; column-parallel differential architecture; column-to-column fixed-pattern noise; correlated double-sampling output circuit; parasitic current effects; passive pixel imager; photodiodes; smear-like effects removal; CMOS image sensors; CMOS process; CMOS technology; Cameras; Charge coupled devices; Charge-coupled image sensors; Circuits; Costs; Pixel; Sensor arrays;
Journal_Title :
Solid-State Circuits, IEEE Journal of
