Title :
Parasitic-compensated switched-capacitor delay lines
fDate :
3/31/1988 12:00:00 AM
Abstract :
Describes a systematic approach to the design of passive parasitic-compensated switched capacitor (SC) delay lines employing well known SC branches. Such delay lines are important building blocks for the implementation of high frequency FIR SC decimators and interpolators with high selectivity amplitude responses
Keywords :
delay lines; signal processing; switched capacitor networks; building blocks; employing well known SC branches; high frequency FIR SC decimators; high selectivity amplitude responses; interpolators; passive parasitic-compensated switched-capacitor delay lines; systematic design approach; video signal processing;
Journal_Title :
Electronics Letters
