DocumentCode :
1417741
Title :
Multiplication by Rational Constants
Author :
De Dinechin, Florent
Author_Institution :
Lab. de l´´Inf. du Parallelisme (LIP), Univ. de Lyon, Lyon, France
Volume :
59
Issue :
2
fYear :
2012
Firstpage :
98
Lastpage :
102
Abstract :
Multiplications by simple rational constants often appear in fixed- or floating-point application code, for instance, in the form of division by an integer constant. The hardware implementation of such operations is of practical interest to reconfigurable computing. It is well known that the binary representation of rational constants is eventually periodic. This brief shows how this feature can be exploited to implement multiplication by a rational constant in a number of additions that is logarithmic in the precision. An open-source implementation of these techniques is provided and is shown to be practically relevant for constants with small numerators and denominators, where it provides improvements of 20% to 40% in area with respect to the state of the art. It is also shown that, for such constants, the additional cost for a correctly rounded result is very small and that correct rounding very often comes for free in practice.
Keywords :
field programmable gate arrays; fixed point arithmetic; floating point arithmetic; FPGA; field- programmable gate arrays; fixed-point application code; floating-point application code; integer constant; rational constant binary representation; reconfigurable computing; Adders; Field programmable gate arrays; Generators; Hardware; Optimization; Table lookup; Floating-point; multiplication by a constant; rational number; reconfigurable computing;
fLanguage :
English
Journal_Title :
Circuits and Systems II: Express Briefs, IEEE Transactions on
Publisher :
ieee
ISSN :
1549-7747
Type :
jour
DOI :
10.1109/TCSII.2011.2177706
Filename :
6126071
Link To Document :
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