Ultralow resistance, selectively silicided VDMOS FETs for high-frequency power switching applications fabricated using sidewall oxide spacer technology

The authors report on the design, fabrication, and performance of a high-cell-density, high-frequency, reliable power FET structure fabricated using self-aligned silicide technology. A high-temperature stable TiSi₂-based power FET process was developed and applied to fabricate scaled 50-V VDMOS FETs. Power FETs with a variety of cell designs to minimize the on-resistance and capacitance, to increase the packing density and to improve device ruggedness were fabricated and tested under DC and transient switching conditions with resistive and inductive loads. For the first time, silicided space power FETs with a specific on-resistance (R_sp) of 0.5 mΩ-cm² and capable of blocking 50 V in the off-state have been demonstrated. Devices with die sizes of 25 mil×25 mil ( I_DS=4 A) and 200 mil×230 mil (I_DS>160 A) and cell density as high as 8×10⁶ cells/in have been successfully fabricated with excellent gate yield. These devices have 10× small gate sheet resistance, 5× smaller capacitance, and 3× smaller R_sp compared to previously best reported power FETs. Significant improvement in the wafer yield was demonstrated for silicided FETs processed based on rapidly thermally annealed silicide. These devices have significantly improved ruggedness characteristics