Title :
A 5-Gb/s decision circuit fabricated in a 1.5- mu m super-self-aligned silicon bipolar IC technology
Author :
Swartz, R.G. ; Archer, V.D. ; Chiu, T.Y. ; Ota, Y. ; Voshchenkov, A.M. ; Long, T. ; Moerschel, K. ; Possanza, W.
Author_Institution :
AT&T Bell Lab., Holmdel, NJ, USA
fDate :
5/1/1991 12:00:00 AM
Abstract :
The design and experimental measurements on a clocked decision circuit for optical communication applications are reviewed. The circuit, fabricated in a 1.5- mu m super-self-aligned silicon bipolar technology, yields a bit-error rate (BER) <10/sup -9/ at a bit rate of 5 Gb/s. At 2.5 Gb/s the small signal input data sensitivity is 10 mV, the clock timing margin is 320 ps (288 degrees phase margin), the output eye-pattern opening is 300 ps (270 degrees phase margin), and the rise/fall times are about 100 ps.<>
Keywords :
bipolar integrated circuits; digital communication systems; elemental semiconductors; emitter-coupled logic; integrated logic circuits; optical communication equipment; silicon; 1.5 micron; 5 Gbit/s; BER; ECL logic configuration; bipolar IC technology; bit-error rate; clocked decision circuit; decision circuit; optical communication applications; super-self-aligned; Application specific integrated circuits; Bipolar integrated circuits; Bit rate; Clocks; Integrated circuit technology; Logic design; Optical fiber communication; Photonic integrated circuits; Power dissipation; Silicon;
Journal_Title :
Microwave and Guided Wave Letters, IEEE
