Wideband flexible-reach techniques for a 0.5–16.3Gb/s fully-adaptive transceiver in 20nm CMOS

This paper describes the design techniques to achieve wideband flexible-reach operation in a fully-adaptive transceiver embedded in a 20nm CMOS FPGA. The receiver utilizes a bandwidth adjustable CTLE for programmable operation over both short-reach and long-reach channels. A modified 11-tap, 1bit speculative DFE topology provides reliable operation across all data rates. The LC PLL feedback divider uses a synchronized CMOS down-counter without a prescaler to achieve a continuous divide ratio of 16-257. The transceiver achieves BER <; 10^-15 over a 28dB loss backplane at 16.3Gb/s and over legacy channels with 10G-KR characteristics at 10.3125Gb/s. The transceiver meets jitter tolerance specifications for both PCIe Gen3 at 8Gb/s and PCIe Gen4 at 16Gb/s in both common-clock and spread-spectrum modes.