An all-digital PWM-based ΔΣ ADC with an inherently matched multi-bit quantizer

An all-digital PWM-based delta-sigma (ΔΣ) ADC is proposed. This system takes advantages of the duration of a pulse, rather than voltage or current, as the analog operand used in its closed-loop operation. Unlike VCO-based ADCs, this ADC as a linear input sampling stage with adequate uncalibrated performance. Furthermore, the architecture allows inherently matched multi-bit quantizer/DAC blocks by taking advantage of delay lines reusable in both quantization and DAC operation. A 3-bit prototype of this ADC in 0.18 μm CMOS process is implemented, tested, and presented. With an OSR of 72 and a bandwidth of 1 MHz, it achieves a dynamic range of 51 dB and SNDR of 49.6 dB while consuming 1.5 mA from a 1.8 V supply. The core occupies an area of 0.0275 mm².