Title :
A 1.2 V 2.64 GS/s 8bit 39 mW skew-tolerant time-interleaved SAR ADC in 40 nm digital LP CMOS for 60 GHz WLAN
Author :
Kundu, Sandipan ; Lu, Julia Hsin-Lin ; Alpman, Erkan ; Lakdawala, Hasnain ; Paramesh, Jeyanandh ; Byunghoo Jung ; Zur, Sarit ; Gordon, Eshel
Author_Institution :
Intel Corp., Hillsboro, OR, USA
Abstract :
A clock-skew tolerant 8-bit 16x time-interleaved (TI) SAR ADC is presented that meets WiGig standard requirements with only background offset and gain calibrations. By using a “correct-by-construction”, timing-calibration-free global bottom-plate sampling scheme, the ADC achieves a sampling rate of 2.64GS/s while maintaining an ENOB of over 6 bits in the entire Nyquist band. The 40nm LP CMOS design dissipates 39mW from 1.2V. The TI-SAR ADC characterized with an integrated receiver front-end achieves -21.44dB EVM at sensitivity with an OFDM/ QAM16 signal.
Keywords :
CMOS digital integrated circuits; OFDM modulation; analogue-digital conversion; quadrature amplitude modulation; wireless LAN; OFDM; QAM16; WLAN; WiGig standard; digital LP CMOS; frequency 60 GHz; integrated receiver front-end; power 39 mW; size 40 nm; skew-tolerant time-interleaved SAR ADC; successive approximation register analog-to-digital converter; voltage 1.2 V; word length 8 bit; CMOS integrated circuits; Calibration; Gain; OFDM; Receivers; Switches; Timing; 802.11ad; ADCs; SAR; Time-interleaving; WiGig; skew-tolerant;
Conference_Titel :
Custom Integrated Circuits Conference (CICC), 2014 IEEE Proceedings of the
Conference_Location :
San Jose, CA
DOI :
10.1109/CICC.2014.6945992
