Title :
A 9-bit 215-MS/s folding-flash time-to-digital converter based on redundant remainder number system
Author :
Bo Wu ; Shuang Zhu ; Yuan Zhou ; Yun Chiu
Author_Institution :
Analog & Mixed-Signal Lab., Univ. of Texas at Dallas, Richardson, TX, USA
Abstract :
A novel folding-flash time-to-digital converter (TDC) based on the remainder number system (RNS) is presented. In this architecture, fine quantization of an input time interval is performed directly with two free-running ring oscillators (RO) without additional circuitry to record the coarse bits. The technique is useful to obtain a high resolution with much fewer delay elements while retaining the same conversion speed compared to the flash counterpart employing delay chains. A proof-of-concept prototype RNS TDC, consisting of 84 delay elements, achieves a resolution of 8.94 bits, or 490 quantization levels. The prototype was fabricated in a 45-nm CMOS process and measured a sample rate of 215 MS/s and an LSB size of 9.4 ps. Without trimming or calibration, the measured differential nonlinearity (DNL) and integral nonlinearity (INL) of the RNS TDC are +0.53/-0.57 and +1.1/-1.1 LSBs, respectively.
Keywords :
CMOS integrated circuits; delay circuits; logic circuits; quantisation (signal); time-digital conversion; CMOS process; TDC; delay chains; delay elements; differential nonlinearity; fine quantization; folding-flash time-to-digital converter; free-running ring oscillators; integral nonlinearity; redundant remainder number system; size 45 nm; word length 8.94 bit; word length 9 bit; CMOS process; Clocks; Delays; Prototypes; Quantization (signal); Radiation detectors; Ring oscillators;
Conference_Titel :
Custom Integrated Circuits Conference (CICC), 2014 IEEE Proceedings of the
Conference_Location :
San Jose, CA
DOI :
10.1109/CICC.2014.6946004
