Title :
CAM2: a highly-parallel two-dimensional cellular automaton architecture
Author :
Ikenaga, Takeshi ; Ogura, Takeshi
Author_Institution :
NTT Integrated Inf. & Energy Syst. Lab., Kanagawa, Japan
fDate :
7/1/1998 12:00:00 AM
Abstract :
Cellular automaton (CA) is a promising computer paradigm that can break through the von Neumann bottleneck. Two-dimensional CA is especially suitable for application to pixel-level image processing. Although various architectures have been proposed for processing two-dimensional CA, there are no compact, practical computers. So, in spite of its great potential, CA is not widely used: This paper proposes a highly-parallel two-dimensional cellular automaton architecture called CAM2 and presents some evaluation results. CAM2 can attain pixel-order parallelism on a single board because it is composed of a CAM, which makes it possible to embed an enormous number processing elements (PEs), corresponding to CA cells, onto one VLSI chip. Multiple-zigzag mapping and dedicated CAM functions enable high-performance CA processing. The performance evaluation results show that 256 k CA cells, which correspond to a 512×512 picture, can be processed by a CAM2 on a single board using deep submicron process technology. The processing speed is more than 10 billion CA cell updates per second. This means that more than a thousand CA-based image processing operations can be done on a 512×512 pixel image at video rates (33 msec). CAM2 will widen the potentiality of CA and make a significant contribution to the development of compact and high-performance systems
Keywords :
cellular automata; content-addressable storage; digital arithmetic; image processing; CAM2; VLSI chip; highly-parallel two-dimensional cellular automaton architecture; image processing; performance evaluation; pixel-level image processing; pixel-order parallelism; von Neumann bottleneck; Application software; Automata; Automation; CADCAM; Computer aided manufacturing; Computer architecture; Image processing; Logic arrays; Multiprocessor interconnection networks; Pixel;
Journal_Title :
Computers, IEEE Transactions on