Title :
A low-power VLSI architecture for full-search block-matching motion estimation
Author :
Do, Viet L. ; Yun, Kenneth Y.
Author_Institution :
Dept. of Electr. & Comput. Eng., California Univ., San Diego, La Jolla, CA, USA
fDate :
8/1/1998 12:00:00 AM
Abstract :
This paper presents an architectural enhancement to reduce the power consumption of the full-search block-matching (FSBM) motion estimation. Our approach is based on eliminating unnecessary computation using conservative approximation. Augmenting the estimation technique to a conventional systolic-architecture-based VLSI motion estimation reduces the power consumption by a factor of 2, while still preserving the optimal solution and the throughput. A register-transfer level implementation as well as simulation results on benchmark video clips are presented
Keywords :
VLSI; approximation theory; data compression; digital signal processing chips; image matching; motion estimation; search problems; shift registers; systolic arrays; video coding; benchmark video clips; conservative approximation; exact distortion; full-search block-matching; low-power VLSI architecture; motion estimation; optimal solution; power consumption reduction; register-transfer level implementation; simulation results; systolic architecture; throughput; video compression; Cameras; Computational complexity; Computational modeling; Computer architecture; Energy consumption; Motion estimation; Throughput; Transform coding; Very large scale integration; Video compression;
Journal_Title :
Circuits and Systems for Video Technology, IEEE Transactions on
