Variation Study and Implications for BJT-Based Thin-Body Capacitorless DRAM

Author

Cho, Min Hee ; Liu, Tsu-Jae King

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., Univ. of California, Berkeley, CA, USA

Volume

33

Issue

3

fYear

2012

fDate

3/1/2012 12:00:00 AM

Firstpage

312

Lastpage

314

Abstract

Variability in back-gated thin-body capacitorless DRAM cell performance is investigated via TCAD simulation. Sources of variability considered include variations in front gate oxide thickness, body thickness, buried oxide thickness, and gate-sidewall spacer width, as well as random dopant fluctuations. Bipolar junction transistor-based cell operation is most sensitive to variations in body thickness and buried oxide thickness. Retention time for an optimized 22 nm-node cell design is predicted to be reduced by approximately 63% due to process-induced variations.

Keywords

DRAM chips; bipolar transistors; integrated circuit design; technology CAD (electronics); BJT-based thin-body capacitorless DRAM; TCAD simulation; back-gated thin-body capacitorless DRAM cell performance; bipolar junction transistor-based cell operation; body thickness; buried oxide thickness; front gate oxide thickness; gate-sidewall spacer width; node cell design; process-induced variation; random dopant fluctuation; size 22 nm; variation study; Computer architecture; Electric potential; Logic gates; Microprocessors; Random access memory; Resource description framework; Sensors; Capacitorless DRAM; retention time; thin body; variation;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/LED.2011.2179002

Filename

6127898