Compact modeling of LDMOS working in the third quadrant

Author

Kejun Xia ; Indana, Harihara ; Gogineni, Usha

Author_Institution

Maxim Integrated, Beaverton, OR, USA

fYear

2014

fDate

15-17 Sept. 2014

Firstpage

1

Lastpage

4

Abstract

This paper presents a method to model the drain current of LDMOS working in the 3^rd quadrant (Vds<;0), which is important for power management IC design. The DIBL effect in 3^rd quadrant is shown to be much more significant than that in 1^st quadrant (Vds>0), and is not captured by the existing LDMOS models. Also, the threshold voltage model is not accurate in 3^rd quadrant, where the drain-body junction is forward biased. Consequently, the existing LDMOS models underestimate the 3^rd quadrant drain current in the sub-threshold region. A drain current expression taking into account these effects for the sub-threshold region is developed and added to the device model through a SPICE component bsource. The modeling accuracy of the drain current in the 3^rd quadrant is significantly improved.

Keywords

MOSFET; integrated circuit design; integrated circuit modelling; semiconductor device models; DIBL effect; LDMOS compact modeling; SPICE component bsource; drain-body junction; drain-induced barrier lowering effect; forward bias; integrated circuit design; laterally diffused metal oxide semiconductor; modeling accuracy; power management IC design; subthreshold region; third quadrant drain current; threshold voltage model; Data models; Equations; Integrated circuit modeling; Junctions; Mathematical model; Semiconductor device modeling; Threshold voltage; MOSFET circuits; Power MOSFET; SPICE; Semiconductor Device Modeling; Simulation;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference (CICC), 2014 IEEE Proceedings of the

Conference_Location

San Jose, CA

Type

conf

DOI

10.1109/CICC.2014.6946028

Filename

6946028