Design Technology co-optimization for N10

Author

Ryckaert, J. ; Raghavan, Praveen ; Baert, R. ; Bardon, M.G. ; Dusa, M. ; Mallik, Abhidipta ; Sakhare, S. ; Vandewalle, B. ; Wambacq, Piet ; Chava, B. ; Croes, Kristof ; Dehan, M. ; Jang, Daeung ; Leray, P. ; Liu, T.-T. ; Miyaguchi, Kenichi ; Parvais, B. ;

Author_Institution

imec, Heverlee, Belgium

fYear

2014

fDate

15-17 Sept. 2014

Firstpage

1

Lastpage

8

Abstract

Design-Technology co-optimization becomes a key knob to enable CMOS scaling. In this work we evaluate the technology options including lithography options as well as device options that are considered to enable N10 scaling by exploring their impact on representative designs such as standard cells, SRAM and analog contexts. This paper illustrates that the design angle needs to be considered early in the development of a technology node. This design assessment and decisions start from lithography constraints and options to power/performance, area and cost, all of which create the Design-Technology Co-Optimization space.

Keywords

CMOS memory circuits; SRAM chips; logic design; optimisation; CMOS scaling; SRAM; analog contexts; design technology cooptimization space; lithography constraints; standard cells; Capacitance; Layout; Lithography; Logic gates; Metals; Resistance; Standards; Analog; CMOS technology; DTCO; EUV; Multiple patterning; SRAM; Standard cell design; finFET;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference (CICC), 2014 IEEE Proceedings of the

Conference_Location

San Jose, CA

Type

conf

DOI

10.1109/CICC.2014.6946037

Filename

6946037