Thermal modeling methodology for efficient system-level thermal analysis

Heat dissipation is assumed to be one of the major challenges in the promising 3D integration technology. Very fine grain structures like TSVs and μ-bumps have considerable impact on heat dissipation properties. However, properly considering individual details of multi-length scale systems is still a challenge for efficient system-level thermal analysis. This paper presents a compact thermal modeling approach targeting fast steady-state and transient thermal analysis. The proposed method associates material homogenization and formal reduction techniques for model simplification, enabling to concurrently handle fine grain structures and constraints from board and package modeling. As a result, a dynamic compact thermal model is achieved offering system-level exploration capabilities. Simulation results of a complete system including a packaged 65nm memory-on-logic 3D circuit, socket and board show the thermal model is able to capture hotspot effects with fast simulation times. Comparisons with temperature measurements on the fabricated circuit demonstrate that accurate system-level thermal model of multi-length scale systems is feasible, showing an average error of 3.96% for steady-state temperature. Secondly, this paper reports an investigation study to show the thermal impact of TSV arrays, vertical stacking and die thickness, showing that 3D integration technology parameters considerably impacts silicon temperature and therefore should be properly modeled for accurate thermal analysis.