4-bit SFQ Multiplier Based on Booth Encoder

Author

Nakamoto, Ryosuke ; Sakuraba, Sakae ; Onomi, Takeshi ; Sato, Shigeo ; Nakajima, Koji

Author_Institution

Res. Inst. of Electr. Commun., Tohoku Univ., Sendai, Japan

Volume

21

Issue

3

fYear

2011

fDate

6/1/2011 12:00:00 AM

Firstpage

852

Lastpage

855

Abstract

We have designed a 2-bit Booth encoder with Josephson Transmission Lines (JTLs) and Passive Transmission Lines (PTLs) by using cell-based techniques and tools. The Booth encoding method is one of the algorithms to obtain partial products. With this method, the number of partial products decreases down to the half compared to the AND array method. We have fabricated a test chip for a multiplier with a 2-bit Booth encoder with JTLs and PTLs. It has a processing frequency of 20 GHz with the bias margin ±25%. The frequency of this circuit increases up to 45 GHz with the bias voltage by 25% increased from the design voltage. The circuit area of the multiplier designed with the Booth encoder method is compared to that designed with the AND array method.

Keywords

multiplying circuits; superconducting logic circuits; superconducting transmission lines; Josephson transmission lines; SFQ multiplier; booth encoder; cell-based technique; frequency 20 GHz; frequency 45 GHz; passive transmission lines; word length 2 bit; word length 4 bit; Adders; Arrays; Clocks; Encoding; Power transmission lines; Resistors; FFT; SFQ; multiplier; superconductive circuits;

fLanguage

English

Journal_Title

Applied Superconductivity, IEEE Transactions on

Publisher

ieee

ISSN

1051-8223

Type

jour

DOI

10.1109/TASC.2010.2095814

Filename

5680955