Invited talk: 3D chip stacking

Summary form only given. 3D chip stacking refers to a vertical stack of chips in which individual chips can communicate with each other through electrical connections. 3D chip stacking has the ability to enhance chip performance by increasing bandwidth, reducing wire delay, and enabling better power management. In true 3D chip stacking, all chips except possibly the topmost chip, contain TSVs (Through Substrate/Silicon Vias). TSVs can be introduced into the silicon CMOS transistor fabrication at a number of points in the manufacturing sequence. Key considerations to determine the optimal introduction point include diameter of the TSV, insulating and conducting materials used in the TSV, and the technology node. TSV fabrication considerations include via etching, insulation, metallization, annealing and capping. The final structure also needs to be evaluated for thermo-mechanical integrity and reliability. Additionally, one must also consider the impact of TSVs on devices. There are different approaches to achieving 3D chip stacking, including die to die stacking, die to wafer stacking, and wafer to wafer stacking. In this talk, we will review various aspects of 3D technology, including fabrication of TSVs, and the performance and reliability of structures with TSVs. We will also review current literature to understand the unique advantages and challenges of 3D chip stacking.