Title :
Architecture and Implementation of a First-Generation Iterative Detection Read Channel
Author :
Galbraith, Richard L. ; Oenning, Travis ; Ross, Michael ; Wilson, Bruce ; Djurdjevic, Ivana ; Park, Jihoon
Author_Institution :
Hitachi Global Storage Technol., Rochester, MN, USA
fDate :
3/1/2010 12:00:00 AM
Abstract :
This paper explores the architecture of a first-generation iterative detection read channel solution that delivers up to an 8% increase in drive capacity compared to previous generation electronics. Using low density parity check (LDPC) coding, detected data is continually improved by a detection structure that implements multiple iterations through a set of soft-input soft-output (SISO) and message-passing (MP) blocks. A specially constructed LDPC code is used to optimize performance in the presence of inter-symbol interference (ISI). Also, Reed-Solomon error correction coding (ECC) is retained for optimal data integrity. A 65 nm technology is used in the implementation of this design.
Keywords :
block codes; data integrity; error correction codes; iterative methods; magnetic recording; parity check codes; LDPC coding; MP block; Reed-Solomon error correction coding; SISO block; data integrity; drive capacity; first generation iterative detection read channel; generation electronics; intersymbol interference; low density parity check coding; message passing block; soft-input soft-output block; CMOS technology; Detectors; Digital circuits; Error correction codes; Hard disks; Intersymbol interference; Maximum likelihood detection; Parity check codes; Reed-Solomon codes; Viterbi algorithm; Iterative detection; low-density parity-check (LDPC); magnetic recording; partial-response maximum-likelihood (PRML);
Journal_Title :
Magnetics, IEEE Transactions on
DOI :
10.1109/TMAG.2009.2038803
