DocumentCode
1419943
Title
High performance real-time neural scheduler for ATM switches
Author
Pousada-Carballo, J.M. ; González-Castaño, F.J. ; Rodríguez-Hernández, P.S. ; García-Palomar, U.M.
Author_Institution
Dept. de Tecnologias de las Commun., Campus Univ. de Vigo, Spain
Volume
4
Issue
11
fYear
2000
Firstpage
372
Lastpage
374
Abstract
Input-buffered asynchronous transfer mode (ATM) packet switches are simpler than output-buffered switches. However, due to HOL blocking, their throughput is poor. Neural schedulers represent a promising solution for high throughput input-buffered switching, but their response time variance is too high for realistic hard real-time constraints. To overcome this problem, we formulate and evaluate a new neural scheduler with bounded response time.
Keywords
asynchronous transfer mode; buffer storage; neural nets; packet switching; real-time systems; ATM switches; HOL blocking; asynchronous transfer mode; bounded response time; hard real-time constraints; high performance real-time neural scheduler; high throughput input-buffered switching; input-buffered packet switches; output-buffered switches; response time variance; Asynchronous transfer mode; Costs; Delay; Hysteresis; Neurons; Packet switching; Processor scheduling; Switches; Telecommunications; Throughput;
fLanguage
English
Journal_Title
Communications Letters, IEEE
Publisher
ieee
ISSN
1089-7798
Type
jour
DOI
10.1109/4234.892206
Filename
892206
Link To Document