DocumentCode
142001
Title
Fault simulation with test switching for static test compaction
Author
Pomeranz, Irith
Author_Institution
Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
fYear
2014
fDate
13-17 April 2014
Firstpage
1
Lastpage
6
Abstract
Static test compaction procedures reduce the number of tests in a given test set without reducing the fault coverage. Static test compaction procedures can use the set or the number of faults detected by each test as guidance. Fault simulation without or with limited fault dropping is needed for producing this information. However, it can be time consuming. To compute the information needed for guiding static test compaction efficiently, this paper describes a fault simulation procedure with fault dropping that attempts to balance the sizes of the sets of detected faults. This is achieved by switching the test being simulated as soon as it detects a fault. Differences in the numbers of detected faults, in spite of the attempt to balance them, is attributed to the relative effectiveness of the tests in detecting target faults. The paper shows that reordering a test set based on the results of fault simulation with test switching is effective when applied prior to forward-looking reverse order fault simulation. In general, the procedure can be used in applications where it is advantageous to balance the sets of detected faults.
Keywords
circuit testing; fault simulation; fault dropping; forward looking reverse order fault simulation; static test compaction; test switching; Approximation methods; Circuit faults; Compaction; Computational modeling; Indexes; Integrated circuit modeling; Switches; Fault simulation; reverse order fault simulation; static test compaction; test generation;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Test Symposium (VTS), 2014 IEEE 32nd
Conference_Location
Napa, CA
Type
conf
DOI
10.1109/VTS.2014.6818738
Filename
6818738
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