A 3.15pJ/cyc 32-bit RISC CPU with timing-error prevention and adaptive clocking in 28nm CMOS

Author

Hiienkari, Markus ; Teittinen, Jukka ; Koskinen, Lauri ; Turnquist, Matthew ; Kaltiokallio, M.

Author_Institution

Technol. Res. Center, Univ. of Turku, Turku, Finland

fYear

2014

fDate

15-17 Sept. 2014

Firstpage

1

Lastpage

4

Abstract

The increased performance from technology scaling makes it feasible to operate digital circuits at ultra-low voltages without the significant performance limitation of earlier process generations. The theoretical minimum energy point resides in near-threshold voltages in current processes, but device and environment variations make it a challenge to operate the circuits reliably. This paper presents an ASIC implementation of a 32-bit RISC CPU in 28nm CMOS employing timing-error prevention with clock stretching to enable it to operate with minimal safety margins while maximizing energy efficiency. Measurements show 3.15pJ/cyc energy consumption at 400mV/2.4MHz, which corresponds to 39% energy savings and 83% EDP reduction compared to operation based on static signoff timing.

Keywords

CMOS digital integrated circuits; clocks; integrated circuit design; integrated circuit reliability; low-power electronics; microprocessor chips; reduced instruction set computing; timing; CMOS; RISC CPU; adaptive clocking; clock stretching; energy efficiency; minimal safety margins; near threshold voltage; size 28 nm; static signoff timing; theoretical minimum energy point; timing error prevention; ultralow voltage operation; word length 32 bit; Adaptation models; CMOS integrated circuits; Central Processing Unit; Clocks; Latches; Pipelines; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference (CICC), 2014 IEEE Proceedings of the

Conference_Location

San Jose, CA

Type

conf

DOI

10.1109/CICC.2014.6946095

Filename

6946095