A coprocessor for clock-mapping-based nearest Euclidean distance search with feature vector dimension adaptability

In this paper, a coprocessor fabricated in 180nm for word-parallel nearest Euclidean distance search is developed based on a distance-clock-mapping concept which results in an area-efficient architecture. Conventionally, the nearest distance search is a computational issue in pattern recognition, which can be completed in O(dn) time by the brute-force search in a d-dimensional space among n reference vectors. For satisfying multiple applications, the dimension flexibility of feature vectors is achieved in the coprocessor with a Dimension Extension Circuit (DEC) for partial distance pre-accumulation. A clock reduction algorithm is used to drastically reduce the exponential increase of worst-case search-clock number with vector-component bit width to only a linear increase. The test chip in 180nm CMOS for parallel search among 32 reference vectors with 8 bit per component achieves low power dissipation of 5.02 mW at 42.9MHz clock frequency and 1.8 V supply voltage. Applications with up to 2048-dimensional feature vectors can be handled by the designed coprocessor.