Gate-induced drain-leakage in buried-channel PMOS-a limiting factor in development of low-cost, high-performance 3.3-V, 0.25-μm technology

Author

Ghodsi, R. ; Sharifzadeh, S. ; Majjiga, J.

Author_Institution

Cypress Semicond., San Jose, CA, USA

Volume

19

Issue

9

fYear

1998

Firstpage

354

Lastpage

356

Abstract

This paper presents a low cost 0.25-μm technology with low standby power for 3.3 V applications. It is shown that as a single gate oxide n-type polysilicon gate technology is scaled, gate-induced drain-leakage (GIDL) in buried-channel PMOS becomes a serious limiting factor in achieving low standby power. The impact of technology choices such as spacer material, spacer width and poly reoxidation conditions on PMOS GIDL is discussed. A technology that successfully limits PMOS leakage is presented.

Keywords

MOS integrated circuits; integrated circuit technology; leakage currents; 0.25 micron; 3.3 V; GIDL; PMOS leakage limitation; buried-channel PMOS; gate-induced drain-leakage; high-performance LV technology; limiting factor; low standby power; low-cost quarter micron technology; poly reoxidation conditions; single gate oxide n-type polysilicon gate technology; spacer material; spacer width; CMOS technology; Costs; Fabrication; Leakage current; MOS devices; Random access memory; Silicon; Space technology; Voltage;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/55.709642

Filename

709642