A 0.4-V, 500-MHz, ultra-low-power phase-locked loop for near-threshold voltage operation

Author

Joung-Wook Moon ; Sung-Geun Kim ; Dae-Hyun Kwon ; Woo-Young Choi

Author_Institution

Yonsei Univ., Seoul, South Korea

fYear

2014

fDate

15-17 Sept. 2014

Firstpage

1

Lastpage

4

Abstract

We present a 500-MHz, ultra-low-power phase-locked loop (PLL) realized with the near-threshold supply voltage of 0.4 V in 65-nm CMOS technology. Our PLL employs a new charge pump (CP) circuit structure that can greatly reduce CP up/down current mismatch and their variation with voltage-controlled oscillator (VCO) control voltages. The PLL consumes only 127.8 μW, which corresponds to power efficiency of 0.256 mW/GHz.

Keywords

CMOS analogue integrated circuits; charge pump circuits; integrated circuit design; integrated circuit testing; low-power electronics; phase locked loops; voltage-controlled oscillators; CMOS technology; CP circuit structure; CP up-down current mismatch; PLL; VCO; charge pump circuit structure; frequency 500 MHz; near-threshold supply voltage; near-threshold voltage operation; power 127.8 muW; power efficiency; size 65 nm; ultra-low-power phase-locked loop; voltage 0.4 V; voltage-controlled oscillator; Charge pumps; Current measurement; Frequency control; Frequency measurement; Phase locked loops; Voltage control; Voltage-controlled oscillators; Automatic frequency calibration (AFC); charge pump; current mismatch; current variation; near-threshold voltage (NTV); phase-locked loop (PLL); ultra-low power; ultra-low voltage (ULV);

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference (CICC), 2014 IEEE Proceedings of the

Conference_Location

San Jose, CA

Type

conf

DOI

10.1109/CICC.2014.6946100

Filename

6946100