Accelerated online error detection in many-core microprocessor architectures

Forthcoming many-core processors are expected to be highly unreliable due to their high design complexity and aggressive manufacturing technology scaling. Online functional testing is an attractive low-cost error detection solution. A functional error detection scheme for many-core architectures can easily employ existing techniques from single-core microprocessors and exploit the available massive parallelism to reduce the total test execution time. However, the straightforward execution of test programs on such parallel architectures does not achieve the maximum theoretical speedup due to severe congestion on common hardware resources, especially the shared memory and the interconnection network. In this paper, we first identify the memory hierarchy parameters of many-core architectures that slow down the execution of parallel test programs. Then, we study typical test programs to identify which of their parts can be parallelized to improve performance. Finally, we propose a test program parallelization methodology for many-core architectures to accelerate online detection of permanent faults. We evaluate the proposed methodology on a popular many-core architecture, Intel´s Single-chip Cloud Computer (SCC) showing an up to 47.6X speedup compared to a serial test program execution approach.