Title :
Testability and reliability enhancement techniques
Author :
Li, Mike ; Roberts, Gordon
Author_Institution :
Altera
Abstract :
This session presents the latest state-of-art testability and reliability enhancement circuit techniques, including design for testability (DFT) techniques for all-digital phase-locked loop (ADPLL), a low-leakage electrostatic discharge (ESD) clamp integrated circuit (IC), measurement ICs for plasma-induced damage (PID) and random telegraph noise (RTN).
Keywords :
Clamps; Discrete Fourier transforms; Frequency measurement; Integrated circuit reliability; Integrated circuits; Temperature measurement;
Conference_Titel :
Custom Integrated Circuits Conference (CICC), 2014 IEEE Proceedings of the
Conference_Location :
San Jose, CA, USA
DOI :
10.1109/CICC.2014.6946114
