• DocumentCode
    142061
  • Title

    Built-in self-test for manufacturing TSV defects before bonding

  • Author

    Di Natale, G. ; Flottes, M.-L. ; Rouzeyre, B. ; Zimouche, Hakim

  • Author_Institution
    LIRMM, Univ. Montpellier II, Montpellier, France
  • fYear
    2014
  • fDate
    13-17 April 2014
  • Firstpage
    1
  • Lastpage
    6
  • Abstract
    In this paper we present a BIST method for TSV pre-bond testing. A dedicated test circuitry per TSV is designed and simulated w.r.t a variety of defects and PVT variations. Based on discharge delay evaluation, the BIST scheme supports concurrent testing, requires small-area implementation and it is robust against PVT variations.
  • Keywords
    built-in self test; concurrent engineering; integrated circuit bonding; integrated circuit manufacture; integrated circuit testing; three-dimensional integrated circuits; BIST method; BIST scheme; PVT variations; TSV prebond testing; bonding; bulti-in self-test; concurrent testing; dedicated test circuitry; defects; discharge delay evaluation; small-area implementation; Built-in self-test; Capacitance; Circuit faults; Delays; Discharges (electric); Through-silicon vias; 3D Pre-Bond Testing; BIST; PVT; Pin-hole; TSV; Void;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Test Symposium (VTS), 2014 IEEE 32nd
  • Conference_Location
    Napa, CA
  • Type

    conf

  • DOI
    10.1109/VTS.2014.6818771
  • Filename
    6818771
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=142061