An area-efficient 12-bit 1.25MS/s radix-value self-estimated non-binary ADC with relaxed requirements on analog components

A 12-bit algorithmic (cyclic) ADC is designed and fabricated in 90nm CMOS, and only occupies as small active area as 0.037mm². With the proposed radix-value self-estimation scheme for a non-binary 1-bit/step architecture, the accuracy requirement on analog components is largely relaxed. Therefore, the implementation of analog circuits such as amplifier and comparator becomes simple, and high-density MOM capacitors can be used to achieve small area. Furthermore, the novel radix-value self-estimation technique can be realized by only simple logic circuits without any extra analog input, so that the total active area of ADC is dramatically reduced. The prototype ADC achieves 62.3dB SNDR at 1.4V power supply and 1.25Msps (20MHz clocking) using a poor DC gain amplifier as low as 45dB and MOM capacitors without any careful layout techniques to improve the capacitor matching. The measured DNL is +0.94/-0.71LSB and INL is +1.9/-1.2LSB at 30kHz input.