A 5mW 250MS/s 12-bit synthesized digital to analog converter

Design automation of analog circuits is becoming inevitable as CMOS technology scales, mainly because the extensive amount of design rule checks cannot be easily handled by manual analog design approaches. This paper presents a low-power 12-bit, 250MS/s digital-to-analog converter (DAC) completely implemented using standard digital design flows and automatic place and route (APR). This is a current-steering DAC, and because the layout of current cells and standard digital cells are APRed together, the resulting custom design effort and time, power, and area are all minimized. Three different calibration algorithms are implemented in order to compensate for the systematic mismatch caused by APR, as well as the inter-die and intra-die variations. The DAC is fabricated in a 65nm CMOS technology, and achieves an SFDR >50dBc at up to a 100MHz input frequency while consuming only 5mW. With minimal (re-) design effort, this DAC achieves a performance that is comparable to that of conventional designs.