DocumentCode
1420956
Title
Comparisons between mesh and hierarchical ring networks for shared-memory multiprocessors
Author
Jiang, Hong ; Hamacher, V.Carl
Author_Institution
Dept. of Computer Science and Engineering, University of Nebraska-Lincoln, Lincoln, Nebraska 68588-0115, U.S.A.
Volume
23
Issue
3
fYear
1998
fDate
7/1/1998 12:00:00 AM
Firstpage
119
Lastpage
125
Abstract
Communication performance comparisons, in terms of message latency, between mesh and hierarchical ring interconnection networks for shared-memory multiprocessors are developed. Traffic in the networks is assumed to consist of the short, fixed-length messages needed for remote-memory read/write operations and cache coherency control. Square-mesh networks with bidirectional links and no end-around connections are compared to two- and three-level hierarchical rings. Wormhole routing is used in the meshes, with messages consisting of / flits, with each flit containing b bits. In the ring networks, each ring segment can contain a complete message of f × b bits. Meshes and three-level rings provide comparable delays for system sizes of up to 200 or 300 processor clusters. The delay comparisons are valid only for the lightly loaded traffic case in which contention and blocking are low. This is the situation in practical shared-memory multiprocessor systems with a low cache miss rate and a high physical locality of reference in the global address space.
Keywords
Approximation methods; Bidirectional control; Delays; Mesh networks; Multiprocessor interconnection; Routing; Switches;
fLanguage
English
Journal_Title
Electrical and Computer Engineering, Canadian Journal of
Publisher
ieee
ISSN
0840-8688
Type
jour
DOI
10.1109/CJECE.1998.7102005
Filename
7102005
Link To Document