Title :
Innovative practices session 10C: Advances in DFT and compression
Author :
Kapur, Rohit ; Pomeranz, Irith
Author_Institution :
Synopsys
Abstract :
This talk will cover different aspects of low-cost and high-quality SOC test to meet varying end application requirements (catalog, automotive, wireless, etc.). While some of the test techniques are well-known, they will be stitched together through illustrations to indicate how test cost can be minimised in the presence of various design and tester constraints, without compromising on the quality. Different digital and analog IP components will be considered as part of the SOC test integration process
Keywords :
Abstracts; Automatic test pattern generation; Discrete Fourier transforms; Manufacturing; Silicon; System-on-chip; Very large scale integration;
Conference_Titel :
VLSI Test Symposium (VTS), 2014 IEEE 32nd
Conference_Location :
Napa, CA, USA
DOI :
10.1109/VTS.2014.6818795
