A methodology for yield-specific leakage estimation in memory

A simulation based pre-silicon leakage estimation methodology for SRAM is proposed. The methodology is easily extended to different voltage and temperature corners and it enables determination of leakage yield. It comprehends the impact of die to die and within die variations. It is used to generate yield specific leakage multipliers to capture impact of variability on leakage. Comparative studies between different bit cells show that relative leakage could be up to 53% different if we do not use the methodology. Finally, results from the methodology are shown to match measured silicon data at 22nm tri-gate CMOS technology within 12% accuracy over the region of interest.