Title :
A Real Time EDAC System for Applications Onboard Earth Observation Small Satellites
Author_Institution :
Centre des Tech. Spatiales (CTS), Arzew, Algeria
Abstract :
Onboard error detection and correction (EDAC) devices aim to secure data transmitted between the central processing unit (CPU) of a satellite onboard computer (OBC) and its local memory. A follow-up is presented here of some low-complexity EDAC techniques for application in random access memories (RAMs) onboard the Algerian microsatellite Alsat-1. The application of a double-bit EDAC method is described and implemented in field programmable gate array (FPGA) technology. The performance of the implemented EDAC method is measured and compared with three different EDAC strategies, using the same FPGA technology. A statistical analysis of single-event upset (SEU) and multiple-bit upset (MBU) activity in commercial memories onboard Alsat-1 is given. A new architecture of an onboard EDAC device for future Earth observation small satellite missions in low Earth orbits (LEO) is described.
Keywords :
artificial satellites; error detection; field programmable gate arrays; random-access storage; satellite computers; statistical analysis; Algerian microsatellite; Alsat-1; CPU; EDAC devices; Earth observation small satellite missions; Earth observation small satellites; FPGA technology; LEO; MBU activity; OBC; RAM; SEU; central processing unit; double-bit EDAC method; field programmable gate array; low Earth orbits; low-complexity EDAC techniques; multiple-bit upset; onboard EDAC device; onboard error detection and correction; random access memories; real time EDAC system; satellite onboard computer; single-event upset; statistical analysis; transmitted data security; Computers; Earth; Low earth orbit satellites; Random access memory; Single event upset; Tunneling magnetoresistance;
Journal_Title :
Aerospace and Electronic Systems, IEEE Transactions on
DOI :
10.1109/TAES.2012.6129661
