Title :
PSRR-enhanced low-dropout regulator
Author :
Huang, Wei-Jen ; Liu, Shen-Iuan
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
A power supply rejection ratio (PSRR) enhancement technique for the low-dropout regulator (LDR) is presented. This proposed LDR with a bandgap reference has been fabricated in a 0.35 μm CMOS process, and its active chip area is 0.1978 mm . From experimental results, the proposed LDR provides a stable output voltage without the output capacitor and achieves over a PSRR of -76 dB at 100 kHz for the output current within 0-150 mA. In addition, the output integrated noise is 21.45 μVrms within a frequency between 22 Hz and 80 kHz.
Keywords :
CMOS integrated circuits; CMOS process; current 0 mA to 150 mA; frequency 22 Hz to 80 kHz; low-dropout regulator; power supply rejection ratio enhancement technique; size 0.35 mum; voltage 21.45 muV;
Journal_Title :
Electronics Letters
DOI :
10.1049/el.2010.2869