PSRR-enhanced low-dropout regulator

A power supply rejection ratio (PSRR) enhancement technique for the low-dropout regulator (LDR) is presented. This proposed LDR with a bandgap reference has been fabricated in a 0.35 μm CMOS process, and its active chip area is 0.1978 mm . From experimental results, the proposed LDR provides a stable output voltage without the output capacitor and achieves over a PSRR of -76 dB at 100 kHz for the output current within 0-150 mA. In addition, the output integrated noise is 21.45 μV_rms within a frequency between 22 Hz and 80 kHz.