Title :
A low phase noise all-digital programmable DLL-based clock generator
Author :
Yu-Lung Lo ; Han-Ying Liu ; Pei-Yuan Chou ; Wei-Bin Yang
Author_Institution :
Dept. of Electron. Eng., Nat. Kaohsiung Normal Univ., Kaohsiung, Taiwan
Abstract :
This paper proposes a low phase noise all-digital programmable DLL-based clock generator. The proposed clock generator is fabricated in a 0.18 μm standard CMOS process with a 1.8 V supply voltage. The proposed digital programmable DLL-based clock generator is easy migration over different processes and low power dissipation. The measurement results show that the input and output frequency ranges can operate 100 MHz ~ 600 MHz and 100 MHz ~ 1.2 GHz, respectively. At 800 MHz, the phase noise is -112.36 dBc @ 1MHz offset frequency. The total power consumption of the clock generator is 23.87 mW, and the active die area of the clock generator is 0.14 mm2.
Keywords :
CMOS digital integrated circuits; clocks; delay lock loops; low-power electronics; phase noise; low phase noise all-digital programmable DLL-based clock generator; low power dissipation; power 23.87 mW; size 0.18 mum; standard CMOS process; voltage 1.8 V; Clocks; Computer architecture; Delay lines; Delays; Generators; Phase noise; Pulse generation; Delay-Lock Loop (DLL); clock generator; digital control delay line; frequency multiplier; multiphase;
Conference_Titel :
Information Science, Electronics and Electrical Engineering (ISEEE), 2014 International Conference on
Conference_Location :
Sapporo
Print_ISBN :
978-1-4799-3196-5
DOI :
10.1109/InfoSEEE.2014.6946185
