Investigation of candidate VRM topologies for future microprocessors

Author

Zhou, Xunwei ; Wong, Pit-Leong ; Xu, Peng ; Lee, Fred C. ; Huang, Alex Q.

Author_Institution

Volterra Co., Fremont, CA, USA

Volume

15

Issue

6

fYear

2000

fDate

11/1/2000 12:00:00 AM

Firstpage

1172

Lastpage

1182

Abstract

By reducing the power supply voltage, faster, lower power consumption, and high integration density data processing systems can be achieved. The current generation high-speed complementary metal-oxide-semiconductor (CMOS) processors (e.g., Alpha, Pentium, Power PC) are operating at above 300 MHz with 2.5 to 3.3 V output range. Future processors will be designed in the 1.1-1.8 V range, to further enhance their speed-power performance. These new generation microprocessors will present very dynamic loads with high current slew rates during transient. As a result, they will require a special power supply, voltage regulator module (VRM), to provide well-regulated voltage. The VRMs should have high power densities, high efficiencies, and good transient performance. In this paper, the critical technical issues to achieve this target for future generation microprocessors are addressed. A VRM candidate topology, interleaved quasisquare-wave (QSW), is proposed. The design, simulation and experimental results are presented

Keywords

AC-DC power convertors; computer power supplies; rectifying circuits; voltage regulators; 1.1 to 1.8 V; 2.5 to 3.3 V; 300 MHz; CMOS processors; candidate VRM topologies; dynamic loads; interleaved quasisquare-wave VRM; microprocessors; power density; power supply; speed-power performance; transient current slew rate; voltage regulator module; CMOS process; Data processing; Energy consumption; Microprocessors; Power generation; Power supplies; Process design; Regulators; Topology; Voltage;

fLanguage

English

Journal_Title

Power Electronics, IEEE Transactions on

Publisher

ieee

ISSN

0885-8993

Type

jour

DOI

10.1109/63.892832

Filename

892832