A 12-Bit 96Msample/s double-data-rate (DDR) pipeline ADC with speed and noise optimization for CMOS image sensors

Author

Sheng Zhang ; Lin Xiaokang ; Guanjing Ren ; Shao Pengzhi

Author_Institution

Shenzhen Grad. Sch., Tsinghua Univ., Shenzhen, China

Volume

3

fYear

2014

fDate

26-28 April 2014

Firstpage

1798

Lastpage

1803

Abstract

In this paper, a 12-bit pipeline ADC with double-data-rate topology is proposed for high-speed CMOS image sensors (CIS). With a unique ping-pang architecture and a pseudo-noise cancellation scheme implemented, the designed ADC achieved a high sampling rate of 96Ms/s and with a good linearity and noise performance. The proposed ADC and image sensor chips are fabricated in the GSMC 0.13μm high-voltage mixed signal CMOS process. According to the simulation result, the SFDR performance is 77dB at 11.4375MHz input and DNL and INL are measured at -0.35LSB/+0.15LSB and -6LSB/+6LSB respectively. The area of the ADC is 1.85mm². Powered with 3.3V power supply, the input range is ±1.8V and the power consumption of the ADC is 70mW.

Keywords

CMOS image sensors; analogue-digital conversion; circuit optimisation; CIS; DDR; GSMC high-voltage mixed signal CMOS process; double-data-rate pipeline ADC; double-data-rate topology; frequency 11.4375 MHz; high-speed CMOS image sensors; noise optimization; ping-pang architecture; power 70 mW; pseudonoise cancellation scheme; size 0.13 mum; speed optimization; voltage 3.3 V; word length 12 bit; Accuracy; CMOS image sensors; Calibration; Noise; Optimization; Pipelines; Power demand; CMOS image sensor (CIS); Double Data Rate (DDR); Noise optimization; Speed optimization; pipeline ADC;

fLanguage

English

Publisher

ieee

Conference_Titel

Information Science, Electronics and Electrical Engineering (ISEEE), 2014 International Conference on

Conference_Location

Sapporo

Print_ISBN

978-1-4799-3196-5

Type

conf

DOI

10.1109/InfoSEEE.2014.6946232

Filename

6946232