DocumentCode :
1422377
Title :
Selection of test nodes for analog fault diagnosis in dictionary approach
Author :
Prasad, V.C. ; Babu, N. Sarat Chandra
Author_Institution :
Dept. of Electr. Eng., Indian Inst. of Technol., New Delhi, India
Volume :
49
Issue :
6
fYear :
2000
fDate :
12/1/2000 12:00:00 AM
Firstpage :
1289
Lastpage :
1297
Abstract :
In this paper, the selection of test nodes has been studied extensively and efficient techniques are proposed. Two broad categories of methods called inclusion methods and exclusion methods are suggested. Strategies are presented to select or delete a test node without affecting the diagnosis capabilities. Examples show that these strategies give a lesser number of test nodes some times. Starting from the fault-wise integer coded table of the test circuit, sorting is employed to generate valid sets and minimal sets. The order of computation of these methods is shown to depend linearly on number of test nodes. It is also proportional to (f log f) where “f” is the number of faults. This is much faster than well-known methods. The concept of minimal set of test nodes is new in analog circuit fault diagnosis. Polynomial time algorithms are proposed in this paper for the first time to generate such sets
Keywords :
analogue circuits; automatic testing; circuit testing; fault diagnosis; analog fault diagnosis; dictionary approach; exclusion methods; inclusion methods; minimal set generation; polynomial time algorithms; test nodes selection; Analog circuits; Circuit faults; Circuit simulation; Circuit testing; Computational modeling; Dictionaries; Fault diagnosis; Polynomials; Sorting; Voltage measurement;
fLanguage :
English
Journal_Title :
Instrumentation and Measurement, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9456
Type :
jour
DOI :
10.1109/19.893273
Filename :
893273
Link To Document :
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