DocumentCode :
1422470
Title :
Electrical modeling and simulation challenges in chip-package codesign
Author :
Cangellaris, Andreas C.
Author_Institution :
Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA
Volume :
18
Issue :
4
fYear :
1998
Firstpage :
50
Lastpage :
59
Abstract :
High-performance, multifunctional systems demand novel, often revolutionary, practices in functional-block integration and packaging. Independent chip, package, and board design will have to give way to a holistic approach
Keywords :
circuit CAD; digital simulation; semiconductor device models; semiconductor device packaging; chip-package codesign; functional-block integration; packaging; simulation; Circuit simulation; Clocks; Computational modeling; Computer simulation; Crosstalk; Delay effects; Integrated circuit interconnections; Microprocessors; Packaging; Power system interconnection;
fLanguage :
English
Journal_Title :
Micro, IEEE
Publisher :
ieee
ISSN :
0272-1732
Type :
jour
DOI :
10.1109/40.710871
Filename :
710871
Link To Document :
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