Title :
Fully depleted dual-gated thin-film SOI P-MOSFETs fabricated in SOI islands with an isolated buried polysilicon backgate
Author :
Denton, Jack P. ; Neudeck, Gerold W.
Author_Institution :
Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
Abstract :
P-channel dual-gated thin-film silicon-on-insulator (DG-TFSOI) MOSFETs have been fabricated with an isolated buried polysilicon backgate in an SOI island formed by epitaxial lateral overgrowth (ELO) of silicon. This structure allows individual operation of both the top and back gates rather than the conventional common backgate structure. When fully-depleted, the buried gate is used to individually shift the top gate threshold voltage (V/sub T/). A linear shift of /spl Delta/V/sub T,top///spl Delta/V/sub G,back/ of 0.5 V/V was achieved with a thin buried oxide. The effective density of interface traps (D/sub it/) for the backgate polysilicon-oxide SOI interface was measured to be 1.8/spl times/10/sup 11/ #/cm/sup 2//spl middot/eV as compared to the substrate-oxide of 1.1/spl times/10/sup 11/ #/cm/sup 2//spl middot/eV.
Keywords :
MOSFET; electron traps; elemental semiconductors; interface states; semiconductor epitaxial layers; semiconductor growth; silicon; silicon-on-insulator; SOI islands; Si-SiO/sub 2/; epitaxial lateral overgrowth; fully depleted dual-gated transistors; interface trap effective density; isolated buried polysilicon backgate; thin-film SOI P-MOSFET; top gate threshold voltage; Etching; Fabrication; Lifting equipment; MOSFET circuits; Planarization; Semiconductor thin films; Silicon on insulator technology; Substrates; Threshold voltage; Transistors;
Journal_Title :
Electron Device Letters, IEEE
