• DocumentCode
    1422990
  • Title

    Computing support-minimal subfunctions during functional decomposition

  • Author

    Legl, Christian ; Wurth, Bernd ; Eckl, Klaus

  • Author_Institution
    Inst. of Electron. Design Autom., Tech. Univ. Munchen, Germany
  • Volume
    6
  • Issue
    3
  • fYear
    1998
  • Firstpage
    354
  • Lastpage
    363
  • Abstract
    The growing popularity of look-up table (LUT)-based field programmable gate arrays (FPGA´s) has renewed the interest in functional or Roth-Karp decomposition techniques. Functional decomposition is a powerful decomposition method that breaks a Boolean function into a set of subfunctions and a composition function. Little attention has so far been given to the problem of selecting good subfunctions after partitioning the input variables into the disjoint bound and free sets. Therefore, the extracted subfunctions usually depend on all bound variables. In this paper, we present a novel decomposition algorithm that computes subfunctions with a minimal number of inputs. This reduces the number of LUT´s and improves the usage of multiple-output SRAM cells. The algorithm iteratively computes subfunctions; in each iteration step it implicitly computes a set of possible subfunctions and finds a subfunction with minimal support. Moreover, our technique finds nondisjoint decompositions, and thus unifies disjoint and nondisjoint decomposition. The algorithm is very fast and yields substantial reductions of the number of LUT´s and SRAM cells.
  • Keywords
    Boolean functions; field programmable gate arrays; iterative methods; logic design; table lookup; Boolean function; Roth-Karp decomposition; SRAM cell; composition function; disjoint decomposition; field programmable gate array; functional decomposition; iterative algorithm; look-up table; nondisjoint decomposition; support-minimal subfunction; technology mapping; Boolean functions; Electronic design automation and methodology; Field programmable gate arrays; Input variables; Iterative algorithms; Partitioning algorithms; Programmable logic arrays; Random access memory; Table lookup; Very large scale integration;
  • fLanguage
    English
  • Journal_Title
    Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1063-8210
  • Type

    jour

  • DOI
    10.1109/92.711307
  • Filename
    711307