DocumentCode :
1423042
Title :
On methods to match a test pattern generator to a circuit-under-test
Author :
Pomeranz, Irith ; Reddy, Sudhakar M.
Author_Institution :
Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
Volume :
6
Issue :
3
fYear :
1998
Firstpage :
432
Lastpage :
444
Abstract :
Autonomous circuits such as linear feedback shift registers (LFSRs) and cellular automats are used as low-cost test pattern generators for circuits testable by pseudo-random patterns. We demonstrate that different LFSRs of the same degree, started from different initial states, may yield significantly different fault coverages and test lengths when used as test pattern generators for a given circuit, especially when the circuit has faults which are hard to detect by a practical number of pseudo-random patterns. Methods to tailor an LFSR to a circuit-under-test are proposed, that attempt to select the most effective LFSR and initial state for the circuit. The first method is based on a learning process that can be applied directly to certain types of circuits. The learning process is also used to establish a collection of (primitive and nonprimitive) LFSRs and initial states, effective for arbitrary circuits. This collection can then be used as a starting point for a genetic optimization procedure aimed at improving the selected LFSR and initial state. The use of an LFSR that can apply complemented as well as uncomplemented test patterns is shown to significantly improve the fault coverage, at the cost of a small area overhead. Experimental results demonstrate the applicability of the proposed approaches to stuck-at faults and to transition faults.
Keywords :
automatic testing; fault diagnosis; genetic algorithms; integrated circuit testing; logic testing; sequential circuits; shift registers; area overhead; autonomous circuits; cellular automats; circuit-under-test; complemented test patterns; fault coverages; genetic optimization procedure; learning process; linear feedback shift registers; pseudo-random patterns; stuck-at faults; test lengths; test pattern generator; transition faults; uncomplemented test patterns; Automatic testing; Circuit faults; Circuit testing; Electrical fault detection; Fault detection; Feedback circuits; Genetics; Linear feedback shift registers; Pattern matching; Test pattern generators;
fLanguage :
English
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1063-8210
Type :
jour
DOI :
10.1109/92.711314
Filename :
711314
Link To Document :
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