Automatic generation of error control codes for computer applications

This paper proposes a methodology, implemented in a tool, to automatically generate the main classes of error control codes (ECC´s) widely applied in computer memory systems to increase reliability and data integrity. New code construction techniques extending the features of previous single error correcting (SEC)-double error detecting (DED)-single byte error detecting (SBD) codes have been integrated in the tool. The proposed techniques construct systematic odd-weight-column SEC-DED-SBD codes with odd-bit-per-byte error correcting (OBC) capabilities to enhance reliability in high speed memory systems organized as multiple-bit-per-chip or card.